1. Field of the Invention
The present invention relates to an FM detecting circuit. More specifically, the present invention relates to an FM detecting circuit for converting an FM signal into two AM signals having a phase difference of 180.degree. through a phase shifting circuit and for detecting the respective AM signals and differentially combining the same.
2. Description of the Prior Art
It has been proposed and put into practical use that an FM signal is applied to a phase shifting circuit or a tuning circuit, whereby the same is converted into two AM signals having a phase difference of 180.degree., whereupon these two AM signals are diode detected and combined to provide a detected output, whereby a low frequency component is withdrawn. One example of such an FM detecting circuit is disclosed in Australian Pat. No. 119,138, which was filed Apr. 27, 1943 as Ser. No. 9103/43, as invented by Paul F. G. Holst and Loren R. Kirkwood and assigned to Amalgamated Wireless (Australasia) Limited, a complete specification being published Oct. 27, 1944.
FIG. 1 is a schematic diagram for explaining an outline of the invention described in the complete specification of the above described Australian Pat. No. 119,138. Referring to FIG. 1, a voltage source 1 serves as a signal source for providing an FM signal, to which a resonance circuit or a tuning circuit comprising an inductor 6 and capacitors 7 and 8 is connected in parallel. The tuning circuit exhibits a parallel resonance by virtue of the inductor 6 and the capacitor 7 and further exhibits a series resonance by virtue of the inductor 6 and the capacitors 7 and 8. The anodes of diodes 2 and 3 are connected to both ends, i.e. the junctions B and A, respectively, of the parallel circuit of the inductor 6 and the capacitor 7. The diodes 2 and 3 are aimed to make diode detection and the cathodes of these are commonly connected through load resistors 4 and 5, while the junction of the load resistors 4 and 5 is further connected to the anode of the diode 2. The cathode of the diode 2, i.e. the junction C is connected through a deemphasis circuit 9 to an audio frequency circuit or a low frequency circuit.
The tuning circuit implemented by the inductor 6 and the capacitors 7 and 8 serve as a phase shifting circuit for converting the FM signal into an AM signal. An intermediate frequency voltage or an FM signal voltage appears between the junction A and the ground. The above described voltage is rectified by means of the diode 3 such that a negative voltage is applied to a load resistor 5. The above described negative voltage is applied to both of the cathode and the anode of the diode 2. The diode 2 detects the intermediate frequency voltage appearing between the junction B and the ground, thereby to provide a positive voltage applied to the load resistor 4. As a result, a voltage between the junction C and the ground proves to a sum of the two individual voltages, wherein the value becomes positive, negative or zero depending on the value of the rectified voltage.
FIG. 2 is a graph explaining a detection characteristic achieved by the FIG. 1 circuit, wherein the abscissa indicates the frequency f and the ordinate indicates a response e. A circuit between the junction B and the ground, i.e. the circuit including the inductor 6 and the capacitors 7 and 8, exhibits a double tuning characteristic. More specifically, one tuning characteristic is attributed to parallel resonance by virtue of the inductance L6 of the inductor 6 and the capacitance C7 of the capacitor 7, wherein the impedance between the junction B and the ground becomes the maximum at the frequency fp. Another tuning characteristic is attributed to series resonance by virtue of the inductance L6 of the inductor 6 and the capacitance C7 of the capacitor 7 and the capacitance C8 of the capacitor 8, wherein the impedance between the junction B and the ground becomes the minimum at the frequency fs. The frequency fs of the series resonance is defined by the following equation (1) and the frequency fp of the parallel resonance is defined by the following equation (2), so that the central frequency fo of the FM detecting circuit is defined by the following equation (3). ##EQU1##
Accordingly, the detecting characteristic of the FIG. 1 circuit is as shown as the curve D in FIG. 2.
An improvement in the FM detecting circuit disclosed in Australian Pat. No. 119,138 has been proposed in German Pat. No. 1906957, for example. German Pat. No. 1906957 was filed Feb. 12, 1969, as invented by Jack Avins and assigned to RCA Corp. (U.S.A.), and published for opposition Sept. 7, 1972.
FIG. 3 is a schematic diagram of a major portion for explaining an outline of the invention disclosed in German Pat. No. 1906957.
Referring to FIG. 3, the reference numeral 100 denotes an integrated circuit portion, wherein terminals 100a, 100b, 100c, 100d, 100e and 100f are provided. The connection terminal 100a is connected to receive an FM signal voltage obtained from an FM signal source 1, such as a sound intermediate frequency voltage in a television receiver. The connection terminal 100f is connected to receive a source voltage Vcc. The connection terminal 100e is connected to the ground. The integrated circuit 100 comprises NPN transistors 102, 103 and 105, 106 connected in a symmetrical fashion. The transistors 102 and 105 are aimed to make diode detection by the use of the base-emitter junction thereof, while the transistors 103 and 106 constitute a differential amplifier 108. The input or the base electrode of the detecting transistor 102 is connected to the connection terminal 100a through the resistor 101 and is also connected to the connection terminal 100c. The base electrode of the other detecting transistor 105 is connected to the connection terminal 100d. The collector electrodes of the detecting transistors 102 and 105 are commonly connected to the connection terminal 100f and the emitter electrodes of the same are connected to the base electrodes of the corresponding transistors 103 and 106, respectively. The emitter electrodes of the pair of transistors 103 and 106 constituting the differential amplifier 108 are commonly connected through the emitter resistors 109 and 110, respectively, while a common constant current source 111 is connected between the common connection and the ground, i.e. the connection terminal 100e. Smoothing capacitors 104 and 107 are connected between the emitter electrodes of the detecting transistors 102 and 105, respectively, and the ground, i.e. the connection terminal 100e. A phase shifting circuit 112 is connected between the connection terminals 100c and 100d, externally of the integrated circuit 100. The phase shifting circuit 112 comprises capacitors 113 and 114 and an inductor 115. A parallel resonance circuit is constituted by the capacitor 114 and the inductor 115 and a series resonance circuit is constituted by the capacitor 113 in addition to the above described capacitor 114 and the inductor 115. Accordingly, FM signals as amplitude modulated (hereinafter referred to as AM signals) having a phase difference of 180.degree. are received at the connection terminals 100c and 100d.
Accordingly, the intermediate frequency signal voltage obtained from the FM signal source 1 is applied to the detecting transistors 102 and 105 as AM signal voltages having a phase difference of 180.degree. by means of the phase shifting circuit 112. The detecting transistors 102 and 105 each diode detect the respective AM signal voltage by means of the respective base-emitter rectifying junctions. The output voltage as detected by the detecting transistor 102 is smoothed by the capacitor 104 and is applied to the base electrode of one transistor 103 of the differential amplifier 108. On the other hand, the output voltage as detected by the detecting transistor 105 is smoothed by the smoothing capacitor 107 and is applied to the base electrode of the other transistor 106 of the differential amplifier 108. More specifically, the base electrode of the transistor 103 is supplied with the output voltage e1 of the detecting transistor 102 and the base electrode of the transistor 106 is supplied with the output voltage e2 of the detecting transistor 105. These output voltages 31 and e2 are shown in FIG. 4A. As seen in FIG. 4A, these output voltages e1 and e2 are of the same magnitude and of the reversed phase at the central frequency f0 of the detecting circuit. Departing in either side from the central frequency f0, the magnitude of one signal voltage increases, while the magnitude of the other signal voltage decreases, for a prescribed range, so that these contain a substantial phase difference of 180.degree.. The output voltage e1 becomes the minimum at the frequency fs, while the output voltage e2 becomes the minimum at the frequency fp. More specifically, the frequency fp is a series resonance frequency of the phase shifting circuit 112 and the frequency fs is a parallel resonance frequency of the phase shifting circuit 112. Accordingly, assuming that the capacitance of the capacitor 113 is C113, the capacitance of the capacitor 114 is C114 and the inductance of the inductor 115 is L115, then the central frequency f0 of the detecting circuit is defined by the following equation (4). ##EQU2## The characteristic of the output from the differential amplifier 108, i.e. the characteristic of the detecting output obtained at the connection terminal 100b of the integrated circuit 100, is shown in FIG. 4B.
The above described German Pat. No. 1906957 is different from the above described Australian Pat. No. 119,138 in the following respects. More specifically, in the Australian Pat. No. 119,138, the AM signals having a phase difference of 180.degree. are individually diode detected and the diode detected outputs are summed up in an analog fashion. By contrast, in the above described German Pat. No. 1906957, the two outputs as diode detected, is subjected to evaluation of a difference therebetween by means of the differential amplifier, whereupon the difference is withdrawn as an output voltage of the detecting circuit. More specifically, in contrast to Australian Pat. No. 119,138, German Pat. No. 1906957 employs a differential amplifier as a characteristic feature.
A counterpart Japanese patent has issued as Japanese Pat. No. 886006. German Pat. No. 1906957 and the Japanese Pat. No. 886006 were granted on those applications filed with a claim to Convention priority based on United States Pat. No. 3,519,944.
As better seen from FIG. 3, German Pat. No. 1906957 employs the smoothing capacitors 104 and 107 in the integrated circuit 100. More specifically, the smoothing capacitors 104 and 107 are formed with a semiconductor junction capacitance of the integrated circuit 100. For this reason, the capacitance values of these capacitors 104 and 107 are liable to be diversified and accordingly the ratio of these capacitances is liable to be asymmetrical. Therefore, the amplitudes of the voltages e1 and e2 applied to the differential amplifier 108 are not necessarily equal to each other. Assuming that the voltages e1 and e2 of different amplitudes are applied to the differential amplifier 108, even in case of a reverse phase of these voltages, a difference AM component is superposed on the output of the differential amplifier 108 and thus on the detected output of the detecting circuit, with the result that an AM suppression characteristic of the FM detecting circuit is degraded. Furthermore, the semiconductor junction capacitances used as the smoothing capacitors 104 and 107 are different from semiconductor chip to semiconductor chip and a detection efficiency is accordingly varied or diversified from integrated circuit to integrated circuit by virtue of such diversified capacitances of the smoothing capacitors. Although capacitance values exceeding a predetermined value are required as those smoothing capacitors 104 and 107 in such detecting circuit, it is difficult or impossible to implement larger capacitances in such detecting circuit as disclosed in German Pat. No. 1906957, wherein semiconductor junction capacitances of the integrated circuit 100 are utilized. Conversely described, in order to achieve a detecting circuit having a sufficient detection efficiency in accordance with the FIG. 3 diagram, it is necessary to increase the capacitance values of the smoothing capacitors 104 and 107, which necessitates an increase of semiconductor junction capacitances constituting these capacitors 104 and 107. In order to increase semiconductor junction capacitances, however, it is necessary to increase the junction areas, as well known, which increases the area of a chip of the integrated circuit 100.